1. Field of the Invention
The present invention relates to a dynamic logic circuit such as a DOMINO logic circuit and a npCMOS logic circuit capable of reducing the static leakage current in its inactive state, and also relates to a self-timed pipelined datapath system which adopts a plurality of combinational circuits therein formed by these dynamic circuits, and controls the active and inactive states thereof along with the data flowing order in response to asynchronous signals.
2. Description of the Related Art
Recently, the LSI circuits installed on communication equipment, for example, battery-operated portable communication devices dissipate more power with an increasing amount of information to be handled on them.
To address this problem, various techniques for lowering power dissipation have been researched and developed. As one example of such a conventional method, a self-timed pipelined datapath system as shown in FIGS. 10 and 12 has been proposed to solve a large power dissipation problem caused by a distribution of clock signals and simultaneously choreographing a huge number of events that take place in a large-scale synchronous system (Jan M. Rabaey, "TIMING ISSUES IN DIGITAL CIRCUITS" in DIGITAL INTEGRATED CIRCUITS, Prentice Hall, 1996).
In the self-timed pipelined datapath system shown in FIG. 10, write enable signals EN1 through EN3 to be applied to registers REG1 through REG3, respectively connected to combinational circuits 11' and 12', are generated in accordance with the state of data processing operation within the respective combinational circuits 11' and 12'. For this reason, a conventional problem of the passing through of unprocessed data due to a clockskew phenomenon can be efficiently avoided, and the same effect can be obtained by a configuration of the self-timed pipelined datapath system shown in FIG. 12. Furthermore, such self-timed pipelined datapath systems are quite effective for reducing power dissipation, as the combinational circuits adopted therein are activated and the issue of signals occurrs only on the arrival of data thereto. Note that the wording "issue" means a state change of a signal from "0" to "1" throughout the specification.
There have been proposed for use as dynamic circuits for the above-mentioned combinational circuits a DOMINO logic circuit (R. Krambeck et al., "High-Speed Compact Circuits with CMOS, "IEEE journal of Solid State Circuits, vol.SSC-17, no.3, pp. 614-619, June 1992) and npCMOS circuit (N. Goncalvez et al., NORA:A Racefree Dynamic CMOS Technique for Pipelined Logic Structures, "IEEE Journal of Solid State Circuits, vol. SSC-18, no.3, pp.261-266, June 1983).
In a DOMINO logic circuit as shown in FIG. 9A, nMOS transistors MN51 and MN52 configure a pull-down network 51, and an nMOS transistor MN55 also configures a pull-down network 53. MP51 and MP52 are pMOS transistors for a precharging operation, and MN53 and MN56 are NMOS transistors for a discharging operation. pMOS transistor MP53 and NMOS transistor MN54 configure a CMOS inverter 52, which transfers the data obtained by the pull-down network 51 at the preceding stage to the pull-down network 53 at the succeeding stage.
In the DOMINO logic circuit as shown above, when the controlling signal ST1 is "0" (meaning the low voltage level throughout the specification), the transistors MP51 and MP52 perform a precharging operation, whereas when it becomes "1" (meaning the high voltage level throughout the specification), a logic operation (sampling operation) is performed.
In a DOMINO logic circuit as shown in FIG. 9B, pMOS transistors MP62 and MP63 configure a pull-up network 61, a pMOS transistor MP66 also configures a pull-up network 63. MP61 and MP65 are pMOS transistors for charging operation, MN61 and MN63 are nMOS transistors for a pre-discharging operation. PMOS transistor MP64 and nMOS transistor MN62 configure a CMOS inverter 62, which transfers the data obtained by the pull-up network 61 at the preceding stage to the pull-up network 63 at the succeeding stage.
In this DOMINO logic circuit, when the controlling signal ST1* (which is an inverted ST1 signal) is "1", a pre-discharging operation is performed by transistors MN61 and MN63, whereas when it becomes "0", a logic operation is performed.
In an npCMOS logic circuit as show in FIG. 9C, pMOS transistors MP72 and MP73 configure a pull-up network 71, an nMOS transistor MN72 configures a pull-down network 72. MP71 is a pMOS transistor for a charging operation, MP74 is a pMOS transistor for a precharging operation, MN71 is a nMOS transistor for a pre-discharging operation and MN73 is a nMOS transistor for a discharging operation.
In this npCMOS logic circuit, when the controlling signal ST1* is "1" (meaning that the ST1 signal is "0"), a pre-discharging operation is performed by the transistors MN71 and a precharging operation is performed by the transistor MP74, whereas when it becomes "0" (meaning that the ST1 becomes "1"), a logic operation is executed.
However, in the case of low supply voltage, if these dynamic circuits are adopted as the combinational circuits in the self-timed pipelined datapath system, and if the MOS transistors composing each of the dynamic circuits have low-threshold voltages so as to comply with the low supply voltage and to accelerate thereof operating speed thereof, a static leakage current is generated when the dynamic circuit is in an inactive state, namely, in a precharging or pre-discharging state. for phenomenon causes power dissipation in the system.